View LT3741_5723934.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt3763 1 3763f pwm dimming pwm 10v/div v sw 50v/div i l 5a/div 5s/div 3763 ta01b typical a pplica t ion fea t ures descrip t ion 60v high current step-down led driver controller the lt ? 3763 is a fixed frequency, synchronous, step-down dc/dc controller designed to accurately regulate output currents up to 20a. the average current mode control- ler will maintain inductor current regulation over a wide output voltage range from 0v to 55v. output current is set by analog voltages on the ctrl pins and an external sense resistor. voltage regulation and overvoltage protec - tion are set with a voltage divider from the output to the fb pin. the switching frequency is programmable from 200khz to 1mhz through an external resistor on the rt pin or with the sync pin and an external clock signal. input and output current sensing provides input current limiting and an accurate measurement of these currents. the fbin pin is provided for applications requiring a peak power tracking function. additional features include an accurate external reference voltage for use with the ctrl pins, an accurate uvlo/ en pin that allows for programmable uvlo hysteresis, a pwm driver for led applications, output voltage fault detection, and thermal shutdown. 20a, pulse width modulated, single led driver a pplica t ions n accurately control input and output current n 3000:1 true color pwm? dimming n 1.5% voltage regulation accuracy n 6% current regulation accuracy n 6v to 60v input voltage range n wide output range up to 55v n <2a shutdown current n control pin for thermal control of load current n input and output current monitor and limit n open, short, and c/10 fault detection n pwm driver output for led applications n thermally enhanced 28-lead fe package n high power architectural lighting n automotive lighting n aviation and marine strobe lights n solar-powered chargers, laser diodes 100f v in 10v to 30v 2.5m 1k 1k 82.5k en/uvlo fbin tg v in boost v ref ctrl1 ctrl2 lt3763 sw bg gnd v c sense + sense ? intv cc 220nf 1.5h 22f 2.5m fb fault 59k 4.7nf 47.5k 3763 ta01 12.1k 2.2f 470k pwmout v out 6v, 20a maximum 220f 2 pwm sync ss 10nf rt 45.3k 84.5k 15.4k 33nf 10 10 47.5k 1f 50k 4.7f ivinn ivinp ivinmon ismon 1nf 1nf 50 50 l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and true color pwm is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7199560, 7321203 and others pending.
lt3763 2 3763f p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , en/uvlo, ivinp, and ivinn ............................... 60v se nse + and sense C ................................................. 60v c trl1, ctrl2, fb, and fbin ...................................... 3v s ync and pwm .......................................................... 6v in tv cc and fa u lt ....................................................... 6v v c , rt, and ss ............................................................ 3v v ref , ivinmon, and ismon ........................................ 3v sw ............................................................................ 60v b oost ...................................................................... 6 6v boost-sw .................................................................. 6v o perating junction temperature (notes 2, 3) lt3763e/lt3763i .............................. C 40c to 125c lt3763h ............................................ C4 0c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) ................... 3 00c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 bg intv cc v in en/uvlo v ref ivinn ivinp ivinmon fault fbin fb gnd ctrl2 ctrl1 gnd boost sw tg pwm_out gnd pwm sync rt ismon v c sense + sense ? ss 29 gnd ja = 30c/w exposed pad (pin 29) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3763efe#pbf lt3763efe#trpbf lt3763fe 28-lead plastic tssop C40c to 125c lt3763ife#pbf lt3763ife#trpbf lt3763fe 28-lead plastic tssop C40c to 125c lt3763hfe#pbf lt3763hfe#trpbf lt3763fe 28-lead plastic tssop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, v en/uvlo = 5v unless otherwise noted. parameter conditions min typ max units input voltage range 6 60 v supply undervoltage lockout from low to high 3.75 4.0 4.25 v v in pin quiescent current non-switching operation shutdown mode v en/uvlo = 1.4v, not switching v en/uvlo = 0v 1.7 0.2 3.5 2 ma a en/uvlo pin threshold (falling edge) 1.47 1.52 1.57 v en/uvlo hysteresis 185 mv en/uvlo pin current en/uvlo = 1.4v, v in = 6v 5 a sync pin threshold (falling edge) 1.4 1.5 1.6 v sync pin hysteresis 675 mv
lt3763 3 3763f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, v en/uvlo = 5v unless otherwise noted. parameter conditions min typ max units pwm pin threshold (falling edge) 1.4 1.5 1.6 v pwm pin hysteresis 675 mv ctrl1 pin current v ctrl1 = 1.5v 20 na ctrl2 pin current v ctrl1 = 1.5v, v ctrl2 = 1.5v, v fbin = 2v 100 na reference reference voltage (v ref pin) l 1.94 2 2.06 v inductor current sensing full range sense + to sense C v ctrl1 = 2v, v ctrl2 > 2v, v ss = v fbin = 2v, v c = 1.2v l 48 51 54 mv sense + pin current v sense + = v sense C = 4v C20 a sense C pin current v sense + = v sense C = 4v, v ctrl1 = 1.5v C40 a internal v cc regulator (intv cc pin) regulation voltage i load = 10ma l 4.8 5 5.2 v current limit v intvcc = 0v 60 ma nmos fet driver non-overlap time tg to bg 42 ns non-overlap time bg to tg 44 ns minimum on-time bg (note 4) 50 ns minimum on-time tg (note 4) 55 ns minimum off-time bg (note 4) 140 ns high side driver switch on-resistance gate pull-up gate pull-down v cboost C v sw = 5v 2.2 1.3 low side driver switch on-resistance gate pull-up gate pull-down v intvcc = 5v 2.2 1 switching frequency r t = 40.2k r t = 200k l 930 180 1000 200 1070 220 khz khz soft-start charging current 11 a voltage regulation amplifier input bias current v fb = 1.3v 750 na g m 850 a/v feedback regulation voltage v sense + = v sense C = v ctrl1 = 2v l 1.188 1.206 1.224 v fault comparator upper fault threshold (fb rising) l 1.137 1.16 1.183 v upper fault threshold hysteresis 40 mv lower fault threshold (fb falling) l 0.24 0.25 0.26 v lower fault threshold hysteresis 40 mv fault pull-down current v fault = 2v, v fb = 0v 8 ma input voltage regulation fbin pin current v fbin = 1.5v 150 na sense voltage (v sense + C v sense C ) v fbin = 1.22v, v sense C = 4v v fbin = 1.26v, v sense C = 4v 10 45 mv mv
lt3763 4 3763f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3763e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3763i is guaranteed to meet performance specifications over the C40c to 125c operating junction temperature range. the lt3763h is guaranteed over the C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. parameter conditions min typ max units output current monitor sense voltage (v sense + C v sense C ) v ismon regulated to 1v, v sense C = 10v v ismon regulated to 200mv, v sense C = 10v 45 5 50 10 55 15 mv mv input current monitor sense voltage (v ivin + C v ivin C ) v ivinmon regulated to 1v, v ivin + = 12v v ivinmon regulated to 200mv, v ivin + = 12v 46 6 50 10 54 14 mv mv input current limit sense voltage (v ivin + C v ivin C ) l 45 50 55 mv pwm driver pwm_out driver on-resistance gate pull-up gate pull-down v intvcc = 5v 2.2 0.9 pwm to pwm_out propagation delay rising falling v intvcc = 5v 11 38 ns ns current control loop g m amp offset voltage v sense C = 4v, v ctrl1 = 0v, v ctrl2 = 2v l C3 0 3 mv input common mode range v cm(low) v cm(high) (note 5) v cm(high) measured from v in to v cm , v sense + = v sense C 0 1.4 v v output impedance 3.5 m g m l 375 475 625 a/v differential gain 1.7 v/mv overvoltage fb overvoltage protection (v fb maximum) 1.515 v overcurrent overcurrent protection (v sense + C v sense C maximum) v sense C = 0v, r t = 200k, v vc = 1.2v 85 mv the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, v en/uvlo = 5v unless otherwise noted. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the minimum on- and off-times are guaranteed by design and are not tested. note 5: the minimum common mode voltage is guaranteed by design and is not tested.
lt3763 5 3763f typical p er f or m ance c harac t eris t ics en/uvlo threshold (falling) en/uvlo current quiescent current (shutdown) v in (v) 6 en/uvlo threshold (v) 1.58 1.64 1.70 3763 g01 1.52 1.46 1.40 42 24 60 v in (v) 6 en/uvlo current (a) 5.0 5.5 6.0 42 3763 g02 4.5 4.0 24 60 temperature (c) ?50 quiescent current (na) 100 1000 10000 75 3763 g03 10 1 0.001 0.01 0.1 ?25 25 50 150125100 0 6v in 12v in 60v in quiescent current (non-switching) v ref voltage v ref current limit v in (v) quiescent current (ma) 3.0 2.0 3763 g04 2.5 1.5 t a = 150c t a = 25c t a = ?50c 6 42 24 60 temperature (c) v ref (v) 2.00 2.01 2.03 2.02 3763 g05 1.99 ?50 75 ?25 25 50 150125100 0 6v in 12v in 60v in 6 42 24 60 v in (v) v ref current limit (ma) 1.2 1.4 1.5 3763 g06 1.0 1.3 1.1 0.9 t a = 150c t a = 25c t a = ?50c rt current limit ss current temperature (c) rt current limit (a) 58 46 70 3763 g07 64 52 40 ?50 75 ?25 25 50 150125100 0 temperature (c) ss current (a) 16 14 12 10 3763 g08 8 ?50 75 ?25 25 50 150125100 0 intv cc current limit i intvcc (ma) 0 v intvcc (v) 4 5 6 50 3763 g09 3 1 2 0 10 20 4030 60
lt3763 6 3763f typical p er f or m ance c harac t eris t ics intv cc load regulation regulated current vs v fb overvoltage threshold overvoltage timeout maximum output voltage v boost C v sw uvlo thresholds intv cc uvlo temperature (c) 3.7 v boost ? v sw (v) 3.8 3.9 4.0 4.1 4.2 3763 g11 ?50 75 ?25 25 50 150125100 0 rising falling 4.0 4.5 3.5 2.5 3.0 ?50 75 ?25 25 50 150125100 0 temperature (c) v intvcc (v) 3763 g12 6v in 12v in 60v in i intvcc (ma) 0 v intvcc (v) 5.00 5.05 5.10 40 3763 g13 4.95 4.90 10 20 30 6050 v fb (v) 1.16 ?50 output current (%) 0 50 100 150 1.17 1.19 1.18 1.20 3763 g18 1.21 temperature (c) v fb (v) 1.47 1.49 1.55 1.53 1.51 3763 g14 1.45 ?50 75 ?25 25 50 150125100 0 temperature (c) timeout (s) 12 13 14 3763 g15 11 10 ?50 75 ?25 25 50 150125100 0 v in ? v out (v) 0 output current (%) 75 100 125 2.0 3763 g17 50 25 0 0.5 1.0 1.5 2.5 v in uvlo temperature (c) v in (v) 4.0 6.0 5.0 3763 g10 3.0 ?50 75 ?25 25 50 150125100 0 overcurrent threshold 0 v sense + ? v sense ? (mv) 20 40 60 100 80 3763 g16 ?50 75 ?25 25 50 150125100 0 temperature (c)
lt3763 7 3763f typical p er f or m ance c harac t eris t ics regulated sense voltage v ctrl1 (v) 0 0 v sense + ? v sense ? (mv) 10 20 30 40 50 60 0.5 1.0 1.5 3763 g25 2.0 nonoverlap time minimum on-time minimum off-time current regulation accuracy current regulation accuracy tg driver r ds(on) bg driver r ds(on) temperature (c) r ds(on) () 3 4 3763 g19 2 1 0 pull-up pull-down ?50 75 ?25 25 50 150125100 0 temperature (c) r ds(on) () 3 4 3763 g20 2 1 0 pull-up pull-down ?50 75 ?25 25 50 150125100 0 ?50 75 ?25 25 50 150125100 0 temperature (c) nonoverlap time (ns) 60 80 3763 g21 40 20 0 bg to tg tg to bg ?50 75 ?25 25 50 150125100 0 temperature (c) minimum on-time (ns) 40 60 80 3763 g23 20 0 hg lg temperature (c) minimum off-time (ns) 120 160 200 3763 g22 80 40 0 hg lg ?50 75 ?25 25 50 150125100 0 v out (v) 0 ?1.0 accuracy (%) ?0.5 0 0.5 1.0 2 4 6 8 10 3763 g26 v ctrl1 = 1.5v v in = 12v v out (v) 0 ?1.0 accuracy (%) ?0.5 0 0.5 1.0 2 4 6 8 10 3763 g27 v ctrl1 = 0.75v v in = 12v temperature (c) frequency (mhz) 0.9 1.2 3763 g24 0.6 0.3 0 1mhz 500khz 200khz ?50 75 ?25 25 50 150125100 0 oscillator frequency
lt3763 8 3763f fault threshold output current sense fault hysteresis input current sense output voltage load regulation input current limit pwm driver r ds(on) c/10 threshold pwm driver delay typical p er f or m ance c harac t eris t ics temperature (c) r ds(on) () 3 4 3763 g28 2 1 0 pull-up pull-down ?50 75 ?25 25 50 150125100 0 temperature (c) delay (ns) 3763 g29 rising falling ?50 75 ?25 25 50 150125100 0 0 10 20 30 40 50 temperature (c) v sense + ? v sense ? (mv) 15 20 3763 g30 10 5 0 ?50 75 ?25 25 50 150125100 0 rising falling temperature (c) v fb (v) 1.2 1.6 3763 g31 0.8 0.4 0 ?50 75 ?25 25 50 150125100 0 upper lower temperature (c) hysteresis (mv) 3763 g32 ?50 75 ?25 25 50 150125100 0 0 25 50 75 v sense + ? v sense ? (mv) 0 0 v ismon (v) 0.5 1.0 1.5 2.0 25 50 75 3763 g33 100 v ivinp ? v ivinn (mv) 0 0 v ivinmon (v) 0.5 1.0 1.5 2.0 25 50 75 3763 g34 100 i load (a) 0 0 v out (v) 2 4 6 8 6 12 18 3763 g36 24 v in = 12v v out = 5v i limit = 20a temperature (c) v ivinp ? v ivinn (mv) 3763 g35 ?50 75 ?25 25 50 150125100 0 45 47 49 51 53 55
lt3763 9 3763f shutdown and recovery pwm dimming 15a load step output voltage load regulation efficiency vs load current efficiency vs load current typical p er f or m ance c harac t eris t ics i load (a) 0 0 v out (v) 8 16 24 32 3 6 9 3763 g37 12 v in = 48v v out = 24v i limit = 10a i load (a) 0 efficiency (%) 100 90 80 95 85 18 3763 g38 24 12 6 v in = 12v v out = 5v i load (a) 0 efficiency (%) 100 90 80 95 85 9 3763 g39 12 6 3 v in = 48v v out = 24v ss 2v/div en/uvlo 5v/div v out 5v/div i l 5a/div 1ms/div 3763 g40 v out 20mv/div ac-coupled i l 10a/div 500s/div 3763 g41 pwm 10v/div v sw 50v/div i l 500ma/div 10s/div 3763 g42 solar powered sla battery charging fault 10v/div v in 500mv/div ac-coupled v out 50mv/div ac-coupled i l 2a/div 50s/div 3763 g43
lt3763 10 3763f bg (pin 1): bg is the bottom fet gate drive signal that controls the state of the external low side power fet. the driver pull-up impedance is 2.2, and pull-down imped- ance is 1. do not force any voltage on this pin. intv cc (pin 2): the intv cc pin provides a regulated 5v output for charging the boost capacitor. intv cc also pro- vides the power for the digital and switching subcircuits. do not force any voltage on this pin. bypass with at least a 22f capacitor to ground. intv cc is current-limited to 50ma. shutdown operation disables the output voltage drive. v in (pin 3): input supply pin. must be locally bypassed with at least a 4.7f low esr capacitor to ground as close as possible to the exposed pad of the package. en/uvlo (pin 4): enable pin. the en/uvlo pin acts as an enable pin and turns on the internal current bias core and sub-regulators at 1.705v and turns off at 1.52v. the pin does not have any pull-up or pull-down, requiring a voltage bias for normal operation. full shutdown occurs at approximately 0.5v. if unused, the enable pin may be tied to v in . v ref (pin 5): buffered 2v reference capable of 0.5ma drive. bypass with at least 1f capacitor to ground. ivinn (pin 6): ivinn is the inverting input of the input current sense amplifier. this pin connects to the drain of the high side n-channel power fet and the input current sense resistor. ivinp (pin 7): ivinp is the noninverting input of the input current sense amplifier. this pin connects to the input supply v in and the input current sense resistor. ivinmon (pin 8): ivinmon is the buffered output of the input current sense amplifier. this pin enables monitoring of the averaged supply current with an output voltage of 20 ? (v ivinp C v ivinn ). the capacitive loading to this pin should be less than 1nf. fault (pin 9): output voltage fault detection pin for shorted or open leds. internal comparators pull down this pin when the fb pin voltage is lower than 0.25v or higher than 1.16v and when the inductor current is less than ten percent of the maximum value. this pin should be pulled up to intv cc with a resistance higher than 10k. fbin (pin 10): the fbin pin enables peak power tracking for solar powered chargers and other similar applications by controlling the output current of the system based on the input voltage. this pin should be tied to v ref if this feature is not used. fb (pin 11): the feedback pin is used for voltage regula - tion and overvoltage protection. the feedback voltage is regulated to 1.206v. when the feedback voltage exceeds 1.515v, the overvoltage lockout prevents switching. p in func t ions
lt3763 11 3763f p in func t ions gnd (pin 12, pin 23, pin 28, exposed pad pin 29): ground. the exposed pad must be soldered to the pcb. ctrl2 (pin 13): thermal control input to reduce the regulated output current. ctrl1 (pin 14): the ctrl1 pin sets the regulated output current. the maximum control voltage is 1.5v. above 1.5v, there is no change in the regulated current. ss (pin 15): the soft-start pin. place an external capacitor to ground to limit the regulated current during start-up conditions. the soft-start pin has an 11a charging cur - rent. when the voltage at this pin is lower than voltages at ctrl1 and ctrl2, it overrides both signals and determines the regulated current. sense C (pin 16): sense C is the noninverting input of the error amplifier for the current regulation loop. the reference current, based on ctrl1, ctrl2, ss or fbin determines the regulated voltage between sense + and sense C . sense + (pin 17): sense + is the inverting input of the error amplifier for the current regulation loop. this pin is connected to an external current sense resistor. the voltage drop between sense + and sense C is measured against the voltage drop across an internal resistor at the input to the current regulation loop. v c (pin 18): a resistor and capacitor connected in series to the v c pin provide the necessary compensation for the stability of the average current loop. typical values are 5k to 60k for the resistor and 2.2nf to 10nf for the capacitor. ismon (pin 19): ismon is the buffered output of the output current sense amplifier. this voltage output enables monitoring the averaged output current of the led driver with a voltage of 20 ? (v sense + C v sense C ). the capacitive loading to this pin should be less than 1nf. rt (pin 20): a resistor from the rt pin to ground sets the switching frequency between 200khz and 1mhz. when using the sync function, set the frequency to be at least 20% lower than the sync pulse frequency. this pin is current-limited to 55a. do not leave this pin open. sync (pin 21): frequency synchronization pin. this pin allows the switching frequency to be synchronized to an external clock. the rt resistor should be chosen to oper - ate the internal clock at 20% slower than the sync pulse frequency. this pin should be grounded when not in use. pwm (pin 22): the input pin for pwm dimming of leds. when low, all switching is terminated and the pwm_out pin is low. this pin should be connected to intv cc when not in use. pwm_out (pin 24): this pin can drive an external fet for pwm dimming of leds. the pull-up and pull-down impedances of the driver are 2.2 and 0.9, respectively. do not force any voltage on this pin. tg (pin 25): tg is the top fet gate drive pin that controls the state of the external high side power fet. the driver pull-up impedance is 2.2, and pull-down impedance is 1.3. do not force any voltage on this pin. sw (pin 26): the sw pin is used internally as the lower rail for the floating top fet gate driver. externally, this node connects the two power fets and the inductor. boost (pin 27): the boost pin provides a floating 5v regulated supply for the top fet gate driver. an external schottky diode is required from the intv cc pin to the boost pin to charge the boost capacitor when the sw pin is near ground.
lt3763 12 3763f b lock diagra m ? + 8 ivinmon 15 ss 13 ctrl2 + ? + ? 10 fbin gnd (12, 23, 28, 29) 1.206v ? + + 14 ctrl1 ? + ? 1.5v 1.5v 90k 11a 3763 bd c ss 10nf 5 v ref v in c ref 2.2f c filt 1f 4 en/uvlo v out r fb2 12.1k r fault 47.5k r fb1 47.5k r filta 1k r filtb 1k current mirror input current monitoring g m = 400a/v 2v reference oscillator internal regulator and uvlo 50k r s 2.5m voltage regulator amp g m = 850a/v control buffer c in1 4.7f c in2 47f c vcc 22f c boost 200nf l1 1h 7 ivinp 6 ivinn 3 v in 2 intv cc boost 25 tg 26 sw 1 bg 21 sync 20 rt 24 pwm_out 22 pwm 27 synchronous controller high side driver low side driver r q s + ? r t 82.5k 18 v c r c 47.5k c c 4.7nf ? + 1.5v 1.206v 1.16v 0.25v + ? 19 ismon + ? 0.1v + ? 17 sense + 16 sense ? 11 fb 9 fault output monitoring c/10 comparator fault detection comparators + ? + ? c out 200f 2 intv cc 3k r sense_in 2.5m g m amp g m = 475a/v r o = 3.5m v cm(high) = v in ? 1.4v figure 1. block diagram
lt3763 13 3763f o pera t ion the lt3763 utilizes fixed frequency, average current mode control to accurately regulate the inductor current inde- pendently from the output voltage. this is an ideal solution for applications requiring a regulated current source. the control loop will regulate the current in the inductor at an accuracy of 6%. if the output reaches the regulation voltage determined by the resistor divider from the output to the fb pin, the inductor current will be reduced by the voltage regulation loop. in voltage regulation, the output voltage has an accuracy of 1.5%. for additional opera- tion information, refer to the block diagram in figure 1. the current control loop has two main inputs, determined by the voltages at the analog control pins, ctrl1 and ctrl2. the lower voltage between ctrl1 and ctrl2 determines the regulated output current. the voltages at ctrl1 and ctrl2 are buffered to produce a reference current set by the voltage across an internal 90k resistor. this reference current produces a reference voltage that the average current mode control loop uses to regulate the inductor current as a voltage drop across the external sense resistor, r s . the outputs of the internal buffers are clamped at 1.5v, limiting the control range of the ctrl1 and ctrl2 pins from 0v to 1.5vcorresponding to a 0mv to 51mv range on r s . the fbin pin provides a third input to the current control loop. this input is dedicated to regulating the input volt- age by controlling the inductor current. inductor current regulation commences when the voltage at the fbin pin rises higher than 1.206v. above 1.206v, the inductor current is linearly increased, providing the maximum current, as determined by the voltages at the ctrl pins, when fbin is at and above 1.26v. when input voltage regulation is not needed, fbin should be tied to v ref to allow the ctrl pins to control the inductor current. the 2v reference provided on the v ref pin allows the use of a resistor voltage divider to the ctrl1 and ctrl2 pins. the current supplied by the v ref pin should be less than 0.5ma. the error amplifier for the average current mode control loop has a common mode lockout that regulates the induc- tor current so that the error amplifier is never operated out of the common mode range. the common mode range is from ground to 1.4v below the v in supply rail. the lt3763 prevents excessive inductor current by trigger - ing overcurrent limit when the inductor current produces a voltage greater than 85mv across the sense + and sense C pins. the current is limited on a cycle-by-cycle basis; switching shuts down as soon as the overcurrent level is reached. overcurrent is not soft-started. the regulated output voltage is set with a resistor divider from the output to the fb pin. the reference for the fb pin is 1.206v. if the output voltage level is high enough to engage the voltage loop, the regulated inductor cur - rent will be reduced. if the voltage at the fb pin reaches 1.515v, an internal overvoltage flag is set, shutting down switching for 12s. the en/uvlo pin functions as a precision shutdown pin. when the voltage at the en/uvlo pin is lower than 1.52v, the internal reset flag is asserted and switching is terminated. full shutdown is guaranteed below 0.5v with a quiescent current of less than 2a. the en/uvlo pin has 185mv of hysteresis built in, and a 5a current source is connected to this pin that allows any amount of hysteresis to be added with a series resistor or resistor divider from v in . alternatively, this pin can be tied directly to v in to reduce the number of off-chip components. during start-up, the ss pin is held low until the internal reset goes low and pwm goes high the first time after a reset event. once the reset is cleared, the capacitor connected to the soft-start pin is charged with an 11a current source. initially, the internal buffers for the ctrl1, ctrl2, and fbin voltages are limited by the voltage at the soft-start pin, and the inductor current reference slowly increases to the level determined by the lowest voltage of those three pins. the rising threshold for thermal shutdown is set at 165c with C5c hysteresis. during thermal shutdown, all switch- ing is terminated, and the part is in reset mode (forcing the ss pin low). the switching frequency is determined by a resistor at the rt pin. this pin is limited to 55a, which limits the switching frequency to approximately 2mhz when the rt pin is shorted to ground. the lt3763 may also be synchronized to an external clock through the use of the
lt3763 14 3763f o pera t ion sync pin which has precise thresholds at 2.175v and 1.5v for rising and falling edges, respectively. lt3763 also features a pwm driver for led dimming. pwm_out is high when the pwm pin voltage is higher than 2.175v, and low when pwm is lower than 1.5v. switching is terminated when pwm is lower than 1.5v. pwm should be tied to intv cc when the pwm function is not needed. the fault pin is pulled down to ground when the voltage at fb becomes less than 0.25v which indicates a short- circuit condition. it is also pulled down to indicate an open-circuit condition when the voltage becomes greater than 1.16v and the inductor current is less than ten percent of the maximum (c/10), or equivalently, when the volt - age between sense + and sense C is less than 5mv. to avoid jitter when recovering from a fault condition, 50mv hysteresis is employed in the comparators. additionally, when the inductor current is lower than c/10, the c/10 comparator disables the low side mosfet regardless of the voltage at fb. the integrated input current and output current monitor - ing functions of the lt3763 allow users to acquire system information such as the input power and output power. the outputs of the current monitors, ivinmon and ismon, range from 0v to 1v when the inputs vary from 0v to 50mv. when using 2.5m sense resistors, for example, these current monitoring amplifiers sense from 0a to 20a. to filter out the switching portion of the currents and measure the average current information, the input pins of the input current monitor, ivinp and ivinn, should connect to the sense resistor through two 1k resistors and a capacitor directly between the ivinp and ivinn pins. the capacitance value can be adjusted according to the switching frequency and the ripple magnitude. the output current monitor employs an internal filter to reduce ripple, and it does not require an external filter, but if one is added, the corner frequency should be higher than the switching frequency. the lt3763 also includes an input current limiting func - tion to regulate the input current to a value determined by the r sense_in resistor. when the voltage drop across the r sense_in resistor approaches 50mv, the inductor current is reduced and regulated so that 50mv is maintained across the ivinp and ivinn pins. a pplica t ions i n f or m a t ion programming inductor current the analog voltage at the ctrl1 pin is buffered and pro- duces a reference voltage, v ctrl , across an internal resistor. the regulated average inductor current is determined by: i o = v ctrl 30 ? r s where r s is the external sense resistor and i o is the aver - age inductor current, which is equal to the output current. figure 2 shows the maximum output current versus r s . the maximum power dissipation in the resistor will be: p rs = 0.05v ( ) 2 r s figure 3 plots the power dissipation in r s , and table 1 lists several resistance values and the corresponding figure 2. r s value selection for regulated output current maximum inductor current and sense-resistor power dis- sipation. susumu, panasonic and vishay offer accurate sense resistors. r s (m) 0 maximum output current (a) 10 20 30 5 15 25 4 8 12 16 3763 f02 20 20 6 10 14 18
lt3763 15 3763f a pplica t ions i n f or m a t ion table 1. sense resistor values maximum output current (a) resistor, r s (m) power dissipation (w) 1 50 0.05 5 10 0.25 10 5 0.50 25 2 1.25 inductor selection size the inductor so that the peak-to-peak ripple current is approximately 30% of the output current. the following equation sizes the inductor for best per - formance: l = v in ? v o ? v o 2 0.3 ? f sw ? i o ? v in ? ? ? ? ? ? where v o is the output voltage, v in is the input voltage, i o is the maximum regulated current in the inductor and f sw is the switching frequency. the overcurrent comparator terminates switching when the voltage between the sense + and sense C pins exceeds 85mv. the saturation current for the inductor should be at least 20% higher than the maximum regulated current. recommended inductor manufacturers are listed in table 2. figure 3. power dissipation in r s table 2. recommended inductor manufacturers vendor website coilcraft www.coilcraft.com sumida www.sumida.com vishay www.vishay.com wrth electronics www.we-online.com nec-tokin www.nec-tokin.com switching mosfet selection the following parameters are critical in determining the best switching mosfets for a given application: total gate charge (q g ), on-resistance (r ds(on) ), gate to drain charge (q gd ), gate-to-source charge (q gs ), gate resistance (r g ), breakdown voltages (maximum v gs and v ds ) and drain current (maximum i d ). the following guidelines provide information to make the selection process easier, and table 3 lists some recommended parts and manufacturers. for both switching mosfets the rated drain current should be greater than the maximum inductor current. use the following equation to calculate the peak inductor current: i max = i o + v in ? v o ? v o 2 2 ? f sw ? l ? v in ? ? ? ? ? ? the rated drain current is temperature dependent, and most data sheets include a table or graph of the rated drain current versus temperature. the rated v ds should be higher than the maximum input voltage (including transients) for both mosfets. as for the rated v gs , the signals driving the gates of the switching mosfets have a maximum voltage of 5v with respect to the source. however, during start-up and recovery conditions, the gate-drive signals may be as low as 3v. therefore, to ensure that the lt3763 recovers properly, the maximum threshold voltage should be less than 2v, and for a robust design, ensure that the rated v gs is greater than 7v. power losses in the switching mosfets are related to the on-resistance, r ds(on) ; gate resistance, r g ; gate-to-drain charge, q gd and gate-to-source charge, q gs . power lost to the on-resistance is an ohmic loss, i 2 r ds(on) , and usually dominates for input voltages less than 15v. power lost while charging the gate capacitance dominates for voltages r s (m) 0 0 power dissipation (w) 0.2 0.6 0.8 1.0 1.4 2 10 14 3763 f03 0.4 1.2 8 18 20 4 6 12 16
lt3763 16 3763f input voltage (v) 0 4 5 7 30 3763 f04a 3 2 10 20 40 1 0 6 mosfet power loss (w) total ohmic transitional input voltage (v) 0 mosfet power loss (w) 1.0 1.5 40 3763 f04b 0.5 0 10 20 30 2.5 2.0 total ohmic transitional a pplica t ions i n f or m a t ion greater than 15v. when operating at higher input voltages, efficiency can be optimized by selecting a high side mosfet with higher r ds(on) and lower q g . the total power loss in the high side mosfet can be approximated by: p loss = ohmic loss + transition loss p loss v o v in ? i o 2 r ds(on) ? t ? ? ? ? ? ? + v in ? i out 5v ? ? ? ? ? ? ? q gd + q gs ( ) ? 2 ? r g + r pu + r pd ( ) ? ? ? ? ? ? ? f sw ? ? ? ? ? ? ? ? where r t is a dimensionless temperature dependent factor in the mosfets on-resistance. using 70c as the maximum ambient operating temperature, r t is roughly equal to 1.3. r pd and r pu are the lt3763 high side gate driver output impedances: 1.3 and 2.2, respectively. a good approach to mosfet sizing is to select a high side mosfet, then select the low side mosfet. the trade-off between r ds(on) , q g , and q gs for the high side mosfet is evident in the following example. v o is equal to 4v. these two n-channel mosfets are rated for a v ds of 40v and mounted in the same package, but with 8 different r ds(on) and 4.5 different q g and q gd : m1: r ds(on) = 2.3m, q g = 45.5nc, q gs = 13.8nc, q gd = 14.4nc, r g = 1 m2: r ds(on) = 18m, q g = 10nc, q gs = 4.5nc, q gd = 3.1nc, r g = 3.5 power loss for both mosfets is shown in figure 4. observe that whereas the r ds(on) of m1 is eight times lower, the power loss at low input voltages is about equal to that of m2, and at high voltages, it is four times higher. power loss within the low side mosfet is almost entirely from the r ds(on) of the fet. select the low side fet with the lowest r ds(on) while keeping the total gate charge q g to 30nc or less. another power loss related to switching mosfet selection is the power lost driving the gates. the total gate charge, q g , must be charged and discharged each switching cycle, so the power lost to the charging of the gates is: p gate = v in t2 glg + q ghg tg sw where q glg is the low side gate charge and q ghg is the high side gate charge. the majority of this loss occurs in the internal ldo within the lt3763: p loss_ldo (v in o7t2 glg + q ghg tg sw whenever possible, utilize a switching mosfet that minimizes the total gate charge to limit the internal power dissipation of the lt3763. some recommended mosfets are listed in table 3. figure 4a. power loss example for m1 figure 4b. power loss example for m2
lt3763 17 3763f table 3. recommended switching fets v in (v) v out (v) i out (a) top fet bottom fet manufacturer 60 4 20 rjk0853dpb rjk0853dpb renesas www.renesas.com 24 4 5 rjk0368dpa rjk0332dpb 48 10 to 35 10 rjk0851dpb rjk0851dpb 12 2 to 4 10 fdms8680 fdms8672as fairchild www.fairchildsemi.com 26 4 20 si7884bdp sir470dp vishay www.vishay.com 24 4 40 psmn4r0-30yl rjk0346dpa nxp/philips www.nxp.com 36 12 10 bsc100n06ls3 bsc100n06ls3 www.infineon.com input capacitor selection the input capacitor should be sized at least 2f for every 1a of output current and placed very close to the high side mosfet. the loop created by the input capacitor, high side mosfet, low side mosfet should be minimized. it should have a ripple current rating equal to half of the maximum output current. additionally, a small 4.7f ceramic capaci - tor should be placed between v in and ground as close as possible to the v in pin and the exposed pad of the package for optimal noise immunity. it is recommended that several low esr (equivalent se- ries resistance) ceramic capacitors be used as the input capacitance, although other capacitors with higher density may be required to reduce board area. only x5r or x7r capacitors maintain their capacitance over a wide range of operating voltages and temperatures. output capacitor selection the output capacitors need to have very low esr to reduce output ripple. a minimum of 20f/a of load current should be used in most designs. the capacitors also need to be surge rated to the maximum output current. to achieve the lowest possible esr, several low esr ceramic capaci- tors should be used in parallel. many lower output voltage applications benefit from the use of high density poscap capacitors, which are easily destroyed when exposed to overvoltage conditions. to prevent this, select poscap capacitors that have a voltage rating that is at least 50% higher than the regulated voltage. note that when dimming, the output voltage increases at the a pplica t ions i n f or m a t ion end of every pulse as the decreasing inductor current flows into the output capacitor. use of a small output capacitor may trigger overvoltage protection through the fb pin. c boot capacitor selection the c boot capacitor must be sized no bigger than 220nf and more than 50nf to ensure proper operation of the lt3763. use 220nf for high current switching mosfets with high gate charge. intv cc capacitor selection the bypass capacitor for the intv cc pin should be larger than 22f to ensure stability, and it should be connected as close as possible to the exposed pad underneath the package. it is recommended that the esr be lower than 50m to reduce noise within the lt3763. for driv - ing mosfets with gate charges larger than 44nc, use 0.5f/nc of total gate charge. soft-start unlike conventional voltage regulators, the lt3763 utilizes the soft-start function to control the regulated inductor current instead of the output voltage. the charging current is 11a and reduces the set current as long as the ss pin voltage is lower than ctrl1 and ctrl2. output current regulation to adjust the regulated load current, an analog voltage is applied to the ctrl1 pin. figure 5 shows the regulated voltage across the sense resistor for control voltages up to v ctrl1 (v) 0 0 v sense + ? v sense ? (mv) 10 20 30 40 50 60 0.5 1.0 1.5 3763 f05 2.0 figure 5. sense voltage vs ctrl voltage
lt3763 18 3763f a pplica t ions i n f or m a t ion figure 6. analog control of inductor current figure 7. input current monitoring voltage vs input current sense voltage figure 8. output current monitoring voltage vs output current sense voltage figure 9. output voltage regulation and overvoltage protection feedback connections 2v. figure 6 shows the ctrl1 voltage created by a voltage divider from v ref to ground. when sizing the resistor divider, please be aware that the v ref pin should have a total load current less than 0.5ma, and that above 1.5v, the control voltage has no effect on the regulated inductor current. setting ctrl1 to 0v does not automatically stop switch - ing. to disable switching, set pwm pin voltage below 1.5v. input current monitoring users can monitor the input current at the ivinmon pin, which produces 0v to 1v as the voltage between ivinp and ivinn varies from 0mv to 50mv, as shown in figure 7. due to the switching of the high side fet, the input current is noisy and monitoring the average input current requires an external filter with 1k resistors connecting ivinp and ivinn to the input current sense resistor r sense_in . choose the capacitor for this filter according to the switching frequency so that the noise is reduced by at least a factor of 100. if the frequency is 500khz, for example, 1f is sufficient, and higher switching frequencies will require a smaller capacitor. a resistor and capacitor may be connected to ivinmon to further filter the noise. with both input and lt3763 v ref r2 r1 3763 f06 ctrl1 output current monitoring, the lt3763 enables users to calculate the overall efficiency of the circuit including the losses in the external components. output current monitoring the lt3763 provides users the capability to monitor the output current as a voltage provided at the ismon pin. the voltage will linearly increase from 0v to 1v as the voltage between sense + and sense C increases from 0mv to 50mv as shown in figure 8. if, for example, a 2.5m resistor is chosen for r s , then a 1v output at ismon will indicate a 20a output current. a resistor and capacitor may be connected to ismon to filter noise. voltage regulation and overvoltage protection the lt3763 uses the fb pin to regulate the output volt - age and to provide an overvoltage lockout to avoid high voltage conditions. the regulated output voltage is pro- grammed using a resistor divider from the output to the fb pin (figure?9). when the output voltage approaches v ivinp ? v ivinn (mv) 0 0 v ivinmon (v) 0.5 1.0 1.5 2.0 25 50 75 3763 f07 100 v sense + ? v sense ? (mv) 0 0 v ismon (v) 0.5 1.0 1.5 2.0 25 50 75 3763 f08 100 lt3763 r2 v out r1 3763 f09 fb
lt3763 19 3763f a pplica t ions i n f or m a t ion the programmed level (1.206v at the fb pin), the voltage error amplifier overrides ctrl1 to set the inductor cur - rent and regulate v out . when the output voltage exceeds 125% of the regulated voltage level (1.515v at the fb pin), the internal overvoltage flag is set, terminating switching. the regulated output voltage must be greater than 1.5v and is set by the equation: v out = 1.206v 1 + r2 r1 ? ? ? ? ? ? fault detection the lt3763 detects that the load has had an open-circuit or short-circuit event indicated by pulling the fault pin to ground. these conditions are detected by comparing the voltage at the fb pin to two internal reference voltages. a short-circuit is defined as v fb lower than 0.25v. in an open-circuit condition, the regulated inductor current will charge the output capacitor, the voltage at fb will begin to increase, and the voltage error amplifier will begin to reduce the inductor current. the open-circuit condition will be indicated at fault when fb is higher than 1.16v and the inductor current is less than ten percent (c/10) of the maximum value set by the sense resistor r s . the output voltage will be regulated as determined by the resistor divider to the fb pin. low current detection when the inductor current decreases to ten percent of the maximum current, the c/10 comparator will also disable the low side gate driver, so the converter will become non-synchronous and automatically transition into dis- continuous conduction mode when the inductor current is low enough relative to the ripple. the low current condition is an essential part of battery charging applications. the lt3763 works well in this ap - plication delivering a constant current to the battery as it charges and then automatically reducing the current to a trickle charge as the battery voltage approaches its fully charged value. in this application, the signal at fault triggered by the low current detection comparator serves as an indicator that the trickle charge phase of charging the battery has begun. programming switching frequency the lt3763 has an operational switching frequency range between 200khz and 1mhz. this frequency is programmed with an external resistor from the rt pin to ground. do not leave this pin open under any condition. the rt pin is also current-limited to 55a. see table 4 and figure?10 for resis - tor values and the corresponding switching frequencies. table 4. switching frequency switching frequency (mhz) r t (k) 1.00 40.2 0.75 53.6 0.50 82.5 0.30 143 0.20 200 switching frequency synchronization the nominal switching frequency of the lt3763 is deter - mined by the resistor from the rt pin to ground and may be set from 200khz to 1mhz. the internal oscillator may also be synchronized to an external clock through the sync pin. the external clock applied to the sync pin must have a logic low below 1.5v and a logic high above 2.175v. the input frequency must be 20% higher than the frequency that would otherwise be determined by the resistor at the rt pin. input signals outside of these specified parameters will cause erratic switching behavior and subharmonic oscillations. synchronization is tested at 500khz with a 200k r t resistor. operation under other conditions is guaranteed by design. when synchronizing to an external r t (k) 0 frequency (mhz) 0.4 0.8 1.2 0.2 0.6 1.0 100 200 300 400 3763 f10 500 500 150 250 350 450 figure 10. frequency vs r t resistance
lt3763 20 3763f a pplica t ions i n f or m a t ion figure 11. pwm driver operation clock, please be aware that there will be a fixed delay from the input clock edge to the edge of the signal at the sw pin. the sync pin must be grounded if the synchronization to an external clock is not required. when sync is grounded, the switching frequency is determined by the resistor r t . pwm driver the lt3763 includes a pwm driver for users who want to control the dimming of leds connected to the output. the driver will pull up the gate of an external n-channel mosfet connected to the pwm_out pin when the voltage at the pwm pin rises above 2.175v and pull down the gate when the voltage falls below 1.5v. when v pwm is lower than 1.5v, switching is terminated and v c is disconnected from the current regulation amplifier. when v pwm is above 2.175v, the inductor current is regulated to the current programmed by the voltage at the ctrl1, ctrl2, or fbin pins. the pull-up driver impedance is 2.2, and the pull-down driver impedance is 0.9. the pwm dimming pulse-width should be longer than two switching cycles. should be tied to intv cc so as not to disable switching. pwm mosfet selection the rated v ds for the pwm mosfet need only be higher than the maximum output voltage. although this permits a mosfet choice with a smaller q g specification than that of the switching mosfets, it will have little effect on efficiency, because the pwm switching frequency will be much lower than that of the switching mosfets. power lost charging the gate of the pwm mosfet will naturally be much lower than the power lost charging the switching mosfets. r ds(on) conduction losses in the pwm mosfet will also be much smaller if the duty cycle of the pwm signal is very low. like the drivers for the switching mosfets, the pwm driver draws power from the intv cc pin, and the choice of mosfet should follow the same recommendations for threshold voltage (less than 2v) and rated v gs (at least 7v). thermal shutdown the internal thermal shutdown within the lt3763 engages at 165c and terminates switching and discharges the soft-start capacitor. when the part has cooled to 160c, the internal reset is cleared and the soft-start capacitor is allowed to charge. shutdown and uvlo the lt3763 has an internal uvlo that terminates switch - ing, resets all synchronous logic, and discharges the soft- start capacitor for input voltages below 4v. the lt3763 also has a precision shutdown at 1.52v on the en/uvlo pin. partial shutdown occurs at 1.52v and full shutdown is guaranteed below 0.5v with less than 2a i q in the full shutdown state. below 1.52v, an internal current source provides 5a of pull-down current to allow for program- mable uvlo hysteresis. the following equations determine the voltage-divider resistors for programming the uvlo voltage and hysteresis as configured in figure 12. r2 = v hyst 5a r1 = 1.52v ? r2 v uvlo ? 1.52v ? ? ? ? ? ? pwm operation when the voltage at pwm is low, all switching of the high and low side mosfets is terminated, and the inductor current will decrease to zero. after pwm increases above the logic threshold, the inductor current ramps up to the regulated value. the ramp time, t d , can be estimated using the following equation: t d = l ? i o v in ? v o which assumes that the output capacitor does not discharge significantly in the time that pwm is low. when the pwm functionality is not desired, the pwm pin 3763 f11 ? + v out pwm_out load pwm 1.5v
lt3763 21 3763f a pplica t ions i n f or m a t ion figure 12. uvlo configuration figure 13. load current derating vs temperature using ntc resistor figure 14. lt3763 average current mode control scheme lt3763 v in r2 v in r1 3763 f12 en/uvlo load current derating using the ctrl2 pin the lt3763 is designed specifically for driving high power loads. in high current applications, derating the maxi- mum current based on operating temperature prevents damage to the load. in addition, many applications have thermal limitations that will require the regulated current to be reduced based on load temperature and/or board temperature. to achieve this, the lt3763 uses the ctrl2 pin to reduce the effective regulated current in the load, which is otherwise programmed by the analog voltage at the ctrl1 pin. the load/board temperature derating is programmed using a resistor divider with a temperature dependant resistance (figure 13). when the load/board temperature rises, the ctrl2 voltage will decrease. when the ctrl2 voltage is lower than voltage at the ctrl1 pin, the regulated current is reduced. lt3763 v ref r ntc r x r v r v r2 r1 (option a to d) 3763 f13 ctrl2 b r ntc a r ntc r x d r ntc c average current mode control compensation the use of average current mode control allows for pre- cise regulation of the inductor current and load current. figure?14 shows the average current mode control loop used in the lt3763, where the regulation current is pro - grammed by a current source and a 3k resistor. to design the compensation network, the maximum com - pensation resistor needs to be calculated. in current mode controllers, the ratio of the sensed inductor current ramp ? + g m error amp modulator load r c l r s 3k v ctrl ? 11a/v c c 3763 f14 to the slope compensation ramp determines the stability of the current regulation loop above 50% duty cycle. in the same way, average current mode controllers require the slope of the error voltage to not exceed the pwm ramp slope during the switch off time. since the closed loop gain at the switching frequency produces the error signal slope, the output impedance of the error amplifier will be the compensation resistor, r c . use the following equation as a good starting point for compensation component sizing: r c = 1k s 1v s l v o s r s s t sw , c c = 2nf s s t sw where t sw is the switching period, l is the inductance value, v o is the output voltage and r s is the sense resistor. for most applications, a 4.7nf compensation capacitor is adequate and provides excellent phase margin with optimized bandwidth. please refer to table 6 for recom - mended compensation values. board layout considerations average current mode control is relatively immune to the switching noise associated with other types of control schemes. nevertheless, the high di/dt loop formed by input capacitors and switching mosfets should be minimized. placing the sense resistor as close as possible to the sense + and sense C pins also helps avoid noise issues. due to sense resistor esl (equivalent series inductance), 10 resistors in series with the sense + and sense C pins with a 33nf ca- pacitor placed between the sense pins are recommended. utilizing a good ground plane underneath the switching
lt3763 22 3763f a pplica t ions i n f or m a t ion components will minimize interplane noise coupling. to dissipate the heat from the switching components, use a table 6. recommended compensation component values (v ctrl2 = 2v) v in (v) v o (v) v ctrl1 (v) i l (a) f sw (khz) l (h) r s (m) r c (k) c c (nf) 12 4 0.75 5 500 2.2 5 54.9 4.7 12 4 1.50 10 500 2.2 5 54.9 4.7 12 5 1.50 20 250 2.2 2.5 44.2 8.2 60 30 0.15 1 500 10 5 15.4 4.7 60 30 1.20 8 500 10 5 15.4 4.7 large area for the switching node while keeping in mind that this negatively affects the radiated noise. typical a pplica t ions 20a, pulse width modulated, single led driver c in2 100f v in 10v to 30v r sense_in 2.5m r filta 1k r filtb 1k r t 82.5k en/uvlo fbin tg v in boost v ref ctrl1 ctrl2 lt3763 sw bg gnd v c sense + sense ? intv cc c boost 220nf l1 1.5h c vcc 22f r s 2.5m fb fault r c 59k c c 4.7nf r fb1 47.5k l1: coilcraft xal1010-152 m1: renesas rjk0365 m2: renesas rjk0453 m3: ir irfh6200 r s : vishay wsl25122l500fea 3763 ta02 r fb2 12.1k c ref 2.2f r ntc 470k m1 m2 pwmout m3 v out 6v, 20a maximum c out 220f 2 d1 pwm sync ss c ss 10nf rt r hot 45.3k r en1 84.5k r en2 15.4k c s 33nf r sa 10 r sb 10 r fault 47.5k c filt 1f 50k c in1 4.7f ivinn ivinp ivinmon ismon 1nf 1nf 50 50 pwm dimming pwm 10v/div v sw 50v/div i l 5a/div 5s/div 3763 ta02b
lt3763 23 3763f typical a pplica t ions 1a, five led driver c in2 4.7f v in 32v to 60v r sense_in 50m r filta 1k r filtb 1k r t 82.5k en/uvlo fbin tg v in boost v ref ctrl1 ctrl2 lt3763 sw bg gnd v c sense + sense ? intv cc intv cc enable c boost 50nf l1 100h c vcc 22f r s 50m fb fault r c 59k c c 4.7nf r fb1 287k l1: coilcraft mss1278-104 m1, m2: renesas rjk1054 r s : vishay wsl2512r0500fea 3763 ta03 r fb2 12.1k c ref 2.2f r ntc 470k m1 m2 pwmout v out 30v, 1a maximum c out 10f 2 d1 d2 d3 d4 d5 pwm sync ss c ss 10nf rt r hot 45.3k c s 33nf r sa 10 r sb 10 r fault 47.5k c filt 1f 50k c in1 1f ivinn ivinp ivinmon ismon
lt3763 24 3763f 3.3a, six-cell (36v) sla battery charger c in2 47f v in 48v r sense_in 15m r filta 1k r filtb 1k r t 82.5k en/uvlo enable fbin tg v in boost v ref ctrl1 ctrl2 lt3763 sw bg gnd v c sense + sense ? intv cc intv cc c boost 220nf l1 12h c vcc 22f r s 15m fb fault r c 8.06k c c 4.7nf r fb1 402k r fb3 178k 12v l1: wrth 74471112 m1, m2: infineon bsc100n06ls3 m3: vishay vn2222ll r s : vishay wsl2512r0150 3763 ta04 r fb2 12.1k c ref 2.2f m1 m2 m3 pwmout v out 45v, 3.3a maximum pwm sync ss c ss 10nf rt c s 33nf r sa 10 r sb 10 r fault 47.5k c filt 1f + 12v + 12v + c in1 1f ivinn ivinp ivinmon ismon typical a pplica t ions 36v sla battery charging fault 10v/div v out 50mv/div ac-coupled i l 2a/div 50s/div 3763 ta04b
lt3763 25 3763f typical a pplica t ions 20a, synchronized, 5v regulator c in2 100f v in 7v to 30v r sense_in 2.5m r filta 1k r filtb 1k r t 121k en/uvlo fbin tg v in boost v ref ctrl1 ctrl2 lt3763 sw bg gnd v c sense + sense ? intv cc intv cc c boost 220nf l1 1.5h c vcc 22f r s 2.5m fb fault r c 59k c c 4.7nf r fb1 38.3k l1: coilcraft xal1010-152 m1: renesas rjk0365 m2: renesas rjk0453 r s : vishay wsl25122l500fea 3763 ta05 r fb2 12.1k c ref 2.2f r ntc 470k m1 m2 pwmout v out 5v, 20a maximum c out 220f 2 pwm sync ss c ss 10nf rt r hot 45.3k c s 33nf r sa 10 r sb 10 r fault 47.5k c filt 1f 3v 0v 500khz c in1 4.7f ivinn ivinp ivinmon ismon r en1 44.2k r en2 15.4k output voltage load regulation efficiency vs load current i load (a) 0 efficiency (%) 100 90 80 95 85 18 3763 ta05c 24 12 6 v in = 12v v out = 5v i load (a) 0 0 v out (v) 2 4 6 8 6 12 18 3763 ta05b 24 v in = 12v v out = 5v i limit = 20a
lt3763 26 3763f typical a pplica t ions 350w white led driver c in2 100f v in 48v r t 200k en/uvlo fbin tg v in boost v ref ctrl1 ctrl2 lt3763 sw bg gnd v c sense + sense ? intv cc intv cc c boost 220nf l1 6h c vcc 22f r s 5m fb fault r c 5k c c 5nf r fb1 931k l1: coiltronics hc2-6r0 m1, m2: renesas rjk0851 r s : vishay wsl25125l000 luminus pt-121 3763 ta06 r fb2 30.9k c ref 2.2f m1 2 m2 2 pwmout v out 37v, 10a maximum c out 10f 6 pwm sync ss c ss 10nf rt c s 1nf r fault 100k 3v 0v 400khz c in1 4.7f ivinn ivinp ivinmon ismon r en1 374k r en2 124k maximum output voltage efficiency vs led current i led (a) 0 efficiency (%) 100 90 80 95 85 9 3763 ta06c 12 6 3 v in = 48v v out = 35v i led (a) 0 0 v out (v) 10 20 30 40 3 6 9 3763 ta06b 12 v in = 48v i limit = 10a
lt3763 27 3763f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. fe28 (eb) tssop rev i 0211 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation eb
lt3763 28 3763f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 1012 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt3743 synchronous step-down led driver controller 92% efficiency, i out to 20a, v in : 5.5v to 36v, i q = 2ma, i sd < 1a, 4mm w 5mm qfn-28, tssop-28e LT3741 synchronous step-down led driver controller 94% efficiency, i out to 20a, v in : 6v to 36v, i q = 1.8ma, i sd < 1a, 4mm w 4mm qfn-20, tssop-20e lt3791 synchronous buck-boost led driver controller 98.5% efficiency, i out to 25a, v in : 4.7v to 60v, tssop-38e 70w, solar energy harvester with maximum power point regulation r fb3 182k m3 enable c in2 100f panel voltage up to 60v 37v v in reg point r sense_in 10m r filta 1k r filtb 1k r t 82.5k en/uvlo fbin tg v in ivinn ivinp boost v ref ctrl1 v ref ctrl2 lt3763 ivinmon ismon sw bg gnd v c sense + sense ? intv cc intv cc c boost 100nf l1 12h c vcc 22f r s 10m fb fault r c 26.1k c c 4.7nf r fb1 121k l1: coilcraft mss1278-123 m1, m2: infineon bsc100n06ls3 m3: vishay vn2222ll r s : vishay wsl2512r0100fea 3763 ta07 r fb2 12.1k c ref 2.2f r ntc 470k m1 m2 pwmout v out 14v maximum 3.6v pwm sync ss c ss 10nf rt r hot 45.3k c s 33nf r sa 10 r sb 10 r fault 47.5k c filt 1f + r fbin1 348k r fbin2 12.1k d1 d2 dn c in1 4.7f solar powered sla battery charging fault 10v/div v in 500mv/div ac-coupled v out 50mv/div i l 2a/div 50s/div 3763 ta07b

▲Up To Search▲

Price & Availability of LT3741

	To Download LT3741 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .